Design for Test Engineer

APPLE INC has the following available in Cupertino , California and various unanticipated locations throughout the USA. Review Architecture and Design Specifications. Extract design features and develop attributes and verification plans. Work with designers to verify DFT implementation and run various checks. Implement test benches, assertions, checkers, generating directed/constrained random tests. Debug failures, run RTL simulations/power aware gate level simulations, supervise bugs, and close coverage.

Build custom testbenches with power aware designs. Generate Collaterals and reports for the test. Perform simulations in RTL, Gate Netlist, and with X-propagation and UPF enabled. Generate Pattern files with DV test scripts. Run playback simulations with the generated patterns. Handle schedules and support multi-functional engineering effort. Assist in verification flows, automation scripts and regressions. Work with test engineers to bring up functional and structural patterns for various Analog IPs and DFT features on Silicon and support further characterization and test time optimization. 40 hours/week.