Master’s degree or foreign equivalent in Electrical Engineering, Electronics Engineering or a related field and Experience and/or education must include: 2 years of experience in the job offered or related occupation. Translating SoC architecture requirements into microarchitecture specifications describing the functionality of the blocks within the subsystem being designed. Coding in Verilog/System Verilog to design subsystems within the System on Chip to meet power/performance and area targets Utilizing programming and/or scripting languages such as C++/Python/Perl to automate design development Defining verification requirements for the subsystems designed such that verification test-cases can be written to ensure correctness of the design Implementing industry standard SoC interconnect protocols such as AHB/AXI, CPU architecture (ARM/RISCV) and peripherals used in SoC development Utilizing source code management tools such as Perforce/GitHub Understanding and editing gate level netlists in order to make logical transformations to fix functional bugs in the design Analyzing timing reports and translating this information into RTL logic changes in order to fix timing issues within the design Analyzing static and dynamic power consumption within the design and making design optimizations to minimize power consumption within the subsystem.