Physical Analysis Engineer

APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Debug flow related issues and make enhancements as appropriate. Work with all aspects of ASIC physical design including floor planning, clock and power distribution. Use industry standard tools to perform analyses such as Apache Redhawk, Voltagestorm, ETS, PT-SI. Perform various electrical analyses at the chip level, including but not limited to Static/Dynamic IR, EM, Noise and Signal EM.

Work multi-functionally with the CAD/technology teams for flow bring up and validation. Collaborate with the implementation team during the entire chip design cycle to drive signoff closure for tape out. Manage schedules and supporting multi-functional engineering effort. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role.