FE Engineering

Apple, Cupertino, California

The role

APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Deliver complex digital IPs for Power Management ICs (PMICs), meeting schedule, area, power, and performance targets. Perform RTL design in SystemVerilog for digital control logic, including the implementation of FSMs and other control structures. Collaborate with cross-functional teams, including Analog Design, Architecture, DFT, and ATE, to develop and finalize precise design specifications.

Synthesize RTL designs into gates and analyze Power, Performance, and Area (PPA) impact using industry-standard tools such as Synopsys Design Compiler, Cadence Genus, and PrimeTime PX. Apply low-power design techniques, including clock and power gating. Perform RTL simulation and functional verification using tools like Cadence Xcelium and Simvision to assess waveforms and ensure correct functionality. Collaborate with the verification team to ensure RTL code meets all feature requirements as defined in the specifications.

Perform Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC) analysis and verification. Manage general design signoff duties, including the cleanup of SDC, CDC, and other constraints files. Utilize scripting languages like Perl and Python for ASIC flow development tasks. Support the Silicon Validation team by explaining design functionality, reviewing test plans, and providing debugging assistance Collaborate with managers and program managers to track project progress. 40 hours/week.

The role

What you need

Master’s degree or foreign equivalent in Electrical and Computer Engineering, Electrical Engineering, Electronics Engineering, or a related field. Experience and/or education must include: Designing digital logic in ASIC using SystemVerilog to implement specific functionalities and features for the ASIC’s required behavior. Simulating ASIC designs using Cadence or Synopsys System Verilog Simulators to verify functional correctness and identify design flaws early before tape out.

Analyzing circuit behavior in Cadence Indago or SimVision waveform viewer to debug design issues, trace signal propagation, and understand timing relationships for the identification and resolution of complex hardware bugs. Synthesizing design into ASIC library gates using Synopsys Design Compiler or Cadence Genus to transform high level RTL code into a gate level netlist for the physical implementation of the chip, optimizing for area, power, and timing.

Using CDC tool to verify clock domain crossings are implemented correctly to ensure reliable data transfer between asynchronous clock domains for the prevention of metastability and functional errors in a multi-clock design. Using RDC tool to verify reset domain crossings are implemented correctly to ensure robustness of the logic during reset scenarios. Performing chip tapeout signoff duties, including the review of constraint files and STA reports to confirm the design meets all timing, power, and area targets for the successful tape out of the silicon.

Generating the power reports under different scenarios and different corners and identify dynamic and leakage power contributors to provide actionable feedback and to improve architecture and RTL design efficiency and ensure to meet Power-Performance-Area (PPA) target. Using the Synopsys PrimeTime tool for RTL and gate-level power estimation and analysis. Working teams to Author the design specifications to define the chip's requirements and ensure alignment for the development of ASICs.

FE Engineering

The role

FE Engineering

The role

What you need

Nice to have

About Apple

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