Digital Verification Engineer

We are looking for a Design Verification Engineer to join our newly formed verification team and own the functional verification of blocks and subsystems in our SoC, including Efficient's proprietary Fabric technology. You'll work alongside senior DV engineers, RTL designers, and architects to build testbenches, close coverage, and find bugs before silicon does. This is a great opportunity to grow your skills while having a real influence on our products and processes as we move from initial product development to market release and scaled volume production.

• Develop and maintain UVM/SystemVerilog testbenches, sequences, and tests for block- and subsystem-level verification.
• Write verification plans from design specifications in collaboration with design and architecture teams.
• Write SystemVerilog assertions and functional coverage models, and drive coverage to closure.