Physical Design Engineer
EnCharge AI, Bangalore +1
What you will do
- End-to-End Ownership: Drive RTL-to-GDSII implementation, including floorplanning, placement, CTS, routing, and physical verification (LVS/DRC/ERC).
- Performance Optimization: Execute high-performance design closure focusing on PPA (Power, Performance, Area) targets in advanced process nodes ( 3nm or below)
- Static Timing Analysis (STA): Perform comprehensive timing closure, including signal integrity, crosstalk analysis, and CPPR (Common Path Pessimism Removal) optimization.
- Power Integrity: Conduct IR-drop analysis (Static/Dynamic) and EM (Electromigration) checks to ensure robust power delivery.
- Innovation: