Power Optimization Engineer
Etched, Cupertino, CA +1
What you will do
- Develop chip power model from chip architecture, estimate chip power from microarchitecture, and devise power saving techniques for product use cases.
- Work closely with Architects, Performance Engineers, Software Engineers, ASIC Design Engineers, and Physical Design teams to implement design for optimal power using advanced power management techniques.
- Estiate and analyze power consumption data at both full-chip and unit levels, guiding ASIC teams to enhance the power efficiency of all functional units both pre-silicon and post silicon. Correlate the estimated power consumption to the measured power.
What you need
- Experience in power optimization using dynamic voltage and frequency scaling techniques, power aware synthesis, glitch power reduction techniques as well as efficient power delivery network implementation.
- Experience with gate-level power optimization through VCD-based and/or FSDB-based power analysis.
- Strong understanding of concepts of energy consumption, estimation, data movement, low power design, and power-saving features.