Power Integrity Engineer

Etched, San Jose

What you will do

Perform pre- and post-layout PDN analysis for high-current ASIC power rails: target impedance profiling, decoupling capacitor selection and placement optimization, and plane resonance analysis.
Execute DC IR-drop and current density simulations; define copper weight, plane shapes, via stitching, and layer allocation requirements for PCB designers.
Conduct AC impedance analysis from VRM output through package and die, including ESR/ESL modeling of the full decoupling network.
Develop and validate VRM models; analyze load transient response, AVP/load-line behavior, and multiphase converter performance against ASIC power specifications.
Perform power-plane thermal co-simulation and work with mechanical teams on thermal-electrical tradeoffs for high-current delivery.

Etched, San Jose

Perform pre- and post-layout PDN analysis for high-current ASIC power rails: target impedance profiling, decoupling capacitor selection and placement optimization, and plane resonance analysis.
Execute DC IR-drop and current density simulations; define copper weight, plane shapes, via stitching, and layer allocation requirements for PCB designers.
Conduct AC impedance analysis from VRM output through package and die, including ESR/ESL modeling of the full decoupling network.
Develop and validate VRM models; analyze load transient response, AVP/load-line behavior, and multiphase converter performance against ASIC power specifications.
Perform power-plane thermal co-simulation and work with mechanical teams on thermal-electrical tradeoffs for high-current delivery.