In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
As a Signal Integrity/Power Integrity (SI/PI) Engineer, you will lead chip and package design, ensuring optimal SI/PI performance and system co-design from concept to production. Collaborating within a cross-functional team, including Chip Design, IP, System Design, software, and vendors, you will drive signal and power design implementations on chip and advanced packages.
The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $163000 - $236000 (USD) + 15% bonus target + equity + benefits
Learn more about benefits at Google [https://www.google.com/about/careers/applications/benefits/].
for High-Performance Computing (HPC) leveraging advanced 2.5D/3D packaging technologies.
Distribution Networks (PDN/power trees), netlists, and routability tradeoffs.
interfaces across IO PHY, SI/PI, and physical design boundaries.
performance and DFM constraints to achieve final package design closure.
developing simulation methodologies to boost modeling accuracy and efficiency.
Science, or a related field, or equivalent practical experience.
Siwave, etc.
high-speed memory and SerDes.
timing analysis (STA), package, and validation teams.
processing tools.
Computer Science, with an emphasis on computer architecture.
stacking architectures.
D2D/chiplets, PCIe, SerDes) and timing budget methodologies.
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checked 4 days agoSource: the company job board. We last checked this job 8 days ago. We first saw it 8 days ago. A job on a job board does not always mean that the team interviews people now.
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