Display Engineering Intern

Reality Labs is building products that make it easier for people to connect with the ones they love most. As a Display Array Modeling Engineering Intern, you will help build pre-silicon simulation models for high pixel-density display arrays to predict front-of-screen artifacts such as crosstalk and mura, and other performance metrics. You will collaborate with cross-functional teams such as panel design and optical engineering. This is a 12 week internship.

Design semiconductor circuits using Cadence Virtuoso Schematic Editor and simulate them using Cadence simulation tools (Spectre/SPICE) Build and validate large-array simulation models using combined distributed and lumped loads, incorporating peripheral circuit blocks and improved test bench setups Analyze circuit layouts and incorporate parasitic extraction results into array-level models to predict coupling to sensitive nodes (e.g., anode, drive transistor gate) Correlate simulated predictions (crosstalk, mura, settling behavior, power/load effects) against measured display data to improve model accuracy Operate optical lab instruments (e.g., microscope, spectrometer, imaging colorimeter, probe station) to measure display KPIs such as crosstalk and mura Develop quantifiable, measurable metrics for display artifacts and automate measurement and data analysis using Python/MATLAB