GFX/Display IP Digital Design Engineer

Contribute to ASIC digital µArchitecture and design Assist performance/power analysis of the design and help meet power and performance targets Work with architects to map algorithms onto the hardware and specify requirements for IP and subsystems integration Collaborate with adjacent teams such as Verification, Physical Design, and Design-for-Test Develop micro-architecture, RTL coding, and design verification for complex IPs Drive IP/sub-system micro-architecture and RTL design in collaboration with DV and PD leads

Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 6+ years of experience as a Hardware Design Engineer for production silicon shipped in volume Experience in digital design µArchitecture, RTL coding, and micro-architecture development Experience communicating technical design decisions and trade-offs to cross-functional partners such as verification, physical design, and architecture teams

Experience micro-architecting and designing IP with heavy fixed-point and/or floating-point data path logic Experience with synthesis, static timing analysis, and timing closure methodologies Experience collaborating with verification or physical design teams during the silicon development cycle Experience with microarchitecture and design optimization for power, performance, and area Experience with at least one procedural programming language (C, C++, Python, etc.) Experience with shell scripting (bash and/or csh) Experience with CDC and RDC analysis Experience with pixel processing pipelines like 2D/3D GFX engines and/or display processing units Demonstrated ability to integrate AI tools to optimize/redesign workflows and drive measurable impact (e.g., efficiency gains, quality improvements) Experience adhering to and implementing responsible, ethical AI practices (e.g., risk assessment, bias mitigation, quality and accuracy reviews) Demonstrated ongoing AI skill development (e.g., prompt/context engineering, agent orchestration) and staying current with emerging AI technologies

$146,000/year to $209,000/year + bonus + equity + benefits