Physical Design and Verification Engineer
Neuralink, South San Francisco, California +1
The role
We are seeking a Senior Physical Design Engineer to own block-to-full-chip implementation and signoff on advanced-node, multi-die 3DIC products. You will drive hierarchical physical design from RTL handoff through tapeout, and lead the multi-physics verification (thermal, mechanical/warpage, and IR/EM) that is unique to stacked-die and chiplet-based systems. This role sits at the intersection of traditional block-level signoff and the emerging discipline of 3D system-level closure.
What you need
- BS/MS in Electrical/Computer Engineering (or equivalent) with 5+ years of physical design experience; MS preferred.