Sr. ASIC Design Engineer (Silicon Engineering)

SpaceX, Austin, TX +3

What you will do

Evaluate architectural trade-offs based on features, performance requirements and system limitations
Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level and deliver the fully verified, synthesis/timing clean design
Work closely with verification team to ensure all aspects of the design are covered and verified
Provide timing constraint for those IPs and support the physical implementation team (synthesis, timing closure, formality check)
Participate in silicon bring-up and validation

Bachelor’s degree in electrical engineering, computer engineering, or computer science
5+ years of experience in RTL implementation

Ability to work extended hours or weekends as needed for mission critical deadlines

SpaceX, Austin, TX +3

Evaluate architectural trade-offs based on features, performance requirements and system limitations
Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level and deliver the fully verified, synthesis/timing clean design
Work closely with verification team to ensure all aspects of the design are covered and verified
Provide timing constraint for those IPs and support the physical implementation team (synthesis, timing closure, formality check)
Participate in silicon bring-up and validation

Bachelor’s degree in electrical engineering, computer engineering, or computer science
5+ years of experience in RTL implementation

Ability to work extended hours or weekends as needed for mission critical deadlines