Sr. ASIC DFT Engineer (Silicon)
SpaceX, Palo Alto, CA +2
What you will do
- Implement and optimize DFT architectures, including scan insertion, compression/decompression logic, memory BIST, and logic BIST, leveraging Siemens Tessent tools
- Integration and verification of Design for Test (DFT) IPs and fabrics within Subsystems
- Set up and run Automatic Test Pattern Generation (ATPG) tools and methodologies, including generating patterns for stuck-at, transition, and path delay fault models, while focusing on pattern compression, diagnosis, and hierarchical test flows.
- Run and debug non-timing and SDF annotated gate-level simulations
- Create and validate DFT patterns for post-silicon bringup and also help with ATE debug through all cycles of silicon characterization