- Bachelor's, Master's, or PhD in Computer Science, Computer Engineering, Electrical Engineering, or a related field, or equivalent experience.
- 8+ years of industry experience in computer networking, system architecture, or high-performance interconnects.
- Strong grasp of network structure and dynamics at scale, including the impact of topology, congestion, and failure modes on distributed workload performance.
- Experience developing or using simulation/modeling environments to evaluate architecture trade-offs.
- Strong multi-functional collaboration skills — comfortable driving alignment across hardware, firmware, and software teams without direct authority over them.
- Clear technical communication, including the ability to explain complex architecture trade-offs to both engineering and non-engineering collaborators.
Ways to Stand Out from the Crowd
- Direct experience with NVLink, NVSwitch, or comparable scale-up interconnect technologies.
- Hands-on experience with high-performance networking transports such as RoCE (RDMA over Converged Ethernet), including concepts low-latency transport, congestion control, and lossless fabric build.
- Experience with memory subsystem architecture, including memory hierarchies, cache coherency, and memory technologies such as HBM, DDR, or LPDDR.
- Working knowledge of large-scale AI model architectures and how they map to network requirements.
- Background in HPC or supercomputing-scale interconnect development.
Your base salary will be determined based on your location, experience, and other objective job-related factors. The expected base salary ranges for this position are: 184,000 USD – 287,500 USD for Level 4; and 224,000 USD – 356,500 USD for Level 5.
You will also be eligible for equity and benefits.
Applications for this job will be accepted at least until November 3, 2026.
This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.