- BS/MS/PhD in Electrical Engineering, Computer Engineering, or equivalent experience.
- 8 years or more of relevant experience in system design and/or ASIC/SoC architecture for GPU, CPU or networking products.
- Deep understanding of communication interconnect protocols such as NVLink, Ethernet, InfiniBand, CXL and PCIe.
- Experience with RDMA/RoCE or InfiniBand transport offload architectures.
- Proven ability to architect multi-GPU/multi-CPU topologies, with awareness of bandwidth scaling, NUMA, memory models, coherency and resilience.
- Experience with hardware-software interaction, drivers and runtimes, and performance tuning for modern distributed computing systems.
- Strong analytical and system modeling skills (Python, SystemC, or similar).
- Excellent cross-functional collaboration skills with silicon, packaging, board, and software teams.
Ways to stand out from the crowd
- Background in system design for AI and HPC.
- Experience with NICs or DPU architecture and other transport offload engines.
- Expertise in chiplet interconnect architectures or multi-node fabrics and protocols for distributed computing.
- Hands-on experience with interposer or 2.5D/3D package co-design.
Your base salary will be determined based on your location, experience, and other objective job-related factors. The expected base salary ranges for this position are: 184,000 USD – 287,500 USD for Level 4; and 224,000 USD – 356,500 USD for Level 5.
You will also be eligible for equity and benefits.
Applications for this job will be accepted at least until November 3, 2026.
This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.