- BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience.
- 8+ years physical design experience, with deep expertise in industry standard tools like ICC2/Innovus, PrimeTime/Tempus, etc.
- Extensive hands‑on P&R experience taking complex blocks or chips to tape‑out with aggressive PPA targets.
- Proven skills in Python, Perl, and TCL flow development.
- Strong problem‑solving skills and self‑motivation, demonstrated by simplifying complex, cluttered environments and modernizing legacy tools and processes.
- Excellent communication and collaboration skills, with a track record of driving consensus and solving complex issues across distributed design, CAD, and R&D teams.
Ways to stand out from the crowd
- Experience collaborating with EDA or internal R&D teams on core engine development, co‑defining features, developing benchmarks and leading validation and deployment.
- Expertise in designing and automating A/B tests and large‑scale regressions, and analyzing large QoR datasets to understand trends and drive root‑cause analysis.
- Background in advanced‑node and large‑scale designs with exposure to advanced‑node challenges (DFM, variability, EM/IR, power integrity).
- Hands‑on experience applying AI/ML or GenAI to physical design, QoR analysis, or flow development will be a strong plus.
If working hands‑on from early architecture and RTL through silicon, and serving as the connector between core developers, methodology teams, and users, excites you, we want to hear from you.
Your base salary will be determined based on your location, experience, and other objective job-related factors. The expected base salary ranges for this position are: 168,000 USD – 264,500 USD for Level 4; and 196,000 USD – 310,500 USD for Level 5.
You will also be eligible for equity and benefits.
Applications for this job will be accepted at least until November 3, 2026.
This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.
