Senior Analog Mixed Signal IC Design Engineer

Key Requirements

• Develop and execute analog and mixed-signal (AMS) designs and verification strategies for complex IC designs including ADCs, DACs, PLLs, LDOs, SerDes, and power‑management blocks.
• Build and maintain behavioral models using Verilog-A, Verilog‑AMS, real‑number modeling (wreal, SV‑RNM), ensuring accurate abstraction and alignment with transistor‑level implementations.
• Perform Spice-level and transistor-level simulations using HSPICE, Spectre, Eldo, and Cadence Virtuoso to validate block‑level and top‑level functionality.
• Develop regression infrastructure and verification dashboards, ensuring thorough functional and analog coverage collection across corners and modes.
• Conduct corner-case analysis, Monte Carlo simulations, noise/mismatch analysis, PVT sweeps, and model correlation to guarantee design robustness.
• Own top-level integration, verification, and sign-off of analog/mixed-signal subsystems and full-chip assemblies using Spectre AMS and Xcelium, ensuring functional correctness, interface robustness, and readiness for tapeout.
• Support DFT strategies for analog/mixed‑signal circuitry, including verification of built‑in test features.
• Collaborate closely with design, modeling, and digital verification teams to ensure alignment between behavioral models and final silicon behavior.
• Participate in silicon bring-up, lab debug, and measurement validation, correlating results with simulation data and refining models as needed.
• Develop scripts and automation tools (Python, Perl, Tcl, MATLAB) to improve simulation efficiency, regression stability, waveform post-processing, and debugging workflows.
• Maintain rigorous version control and continuous integration practices.

Required Qualifications

• Bachelor's, master’s or PhD in Electrical Engineering or related field
• 5+ years of experience in analog/mixed-signal design, verification, AMS modeling, and transistor‑level analysis.
• Strong proficiency with Verilog-A, Verilog-AMS, and real-number modeling techniques (wreal, SV‑RNM).
• Hands-on experience with Cadence Virtuoso, Spectre, Eldo, HSPICE, Cadence AMS Designer, Spectre AMS, and Xcelium.
• Solid understanding of analog/mixed-signal systems such as ADCs, DACs, PLLs, LDOs, SerDes, and PMIC architectures.
• Experience in lab measurements, silicon debug, and correlating real hardware behavior with simulation.
• Proficiency with scripting languages (Python, Perl, Tcl, MATLAB) for automation, data processing, and regression management.
• Comfortable working with Git, CI pipelines (e.g., Jenkins), and multi-disciplinary engineering teams.
• Strong communication skills, problem-solving ability, and ownership of verification quality from block-level through tape-out and silicon validation.

Physical Requirements

Must be sufficiently mobile to work within confined spaces and have both visual and hearing acuity

You will be a senior individual contributor on a cutting-edge quantum control electronics team, designing analog and mixed-signal ICs that directly enable scalable quantum computing. In this role, you will contribute to the architecture, implementation, integration, and verification of complex cryogenic CMOS circuits. You will apply deep hands-on expertise in analog/mixed-signal circuit design, together with strong design-verification practices, to deliver high-performance, reliable, and manufacturable silicon.

Don’t meet every single requirement? Studies have shown that some people are less likely to apply to jobs unless they meet every single desired qualification. At HRL, we are dedicated to building a diverse, inclusive, and authentic workplace, so if you’re excited about this role but your past experience doesn’t align perfectly with every qualification in the job description, we encourage you to apply anyway. You may be just the right candidate for this or other roles.

We are proud to be an EEO/AA employer M/F/D/V. We maintain a drug-free workplace and perform pre-employment substance abuse testing.

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• Pay Range: $154,500 - $197,900
• Our salary ranges are determined by role, level, and location (California). The range displayed on each job posting reflects the target range for new hire salaries for the position. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range during the hiring process.
• Benefits: HRL offers a generous and very competitive total compensation and benefits package. Our Regular/Full Time benefits include medical, dental, vision, life insurance, 401K match, gym facilities, PTO, Sick time, upward mobility, and an exciting and challenging work environment.
• For more information about our company benefit offerings please visit: https://www.hrl.com/careers/benefits