Working on RAS, PCIe, Memory, MCA, CXL and Micro-Controller related failures with customers to get problems resolved Collaboration with AMD global teams to identify best solutions Providing validation and debug recommendations to customers for validation, new features and debug related questions Utilizing debug tools (e.g., debug scripts, protocol analyzers, SCAN and JTAG tools etc.) to narrow down and root cause customer failures Debugging issues found during the process, bring-up, validation, and production phases of SOC programs Engaging in other software/hardware/design teams Leading task force and collaborative approach with multiple teams PREFERRED EXPERIENCE: 10+ years of total experience inclusive of one or multiple of the following areas: RAS (reliability, availability and serviceability) validation and debug.
PCIe/CXL functional and protocol (e.g. Gen1~Gen6) debug, including PCIe/CXL IP bring up, validation and analysis. Memory functional and protocol validation and/or debug. MCA/MCE (Machine check architecture and exception) validation and debug. Experience of post silicon validation methodologies Experience of developing programming languages such as Python scripts Experience of handling various high-speed test and measurement equipment such as protocol analyzer and scope Experience of X86 micro architecture Programming/scripting skills (e.g.
Python, C++, Perl, Ruby etc). Debug techniques and methodologies ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering LOCATION: Austin, TX Bellevue, WA Santa Clara, CA This role is not eligible for visa sponsorship.