Memory Design Engineer
Intel, US, Texas, Austin
The role
Intel's Corporate Memory Organization (CMO) within Design Technology Platform (DTP) drives development of Memory Compilers on Intel's leading-edge process technologies. The organization is responsible for architecting, designing and delivering high-performance and energy-efficient embedded memory IP that maximize silicon performance, optimize density, and maximize manufacturing yield across Intel Products and Intel Foundry platforms.
As a Circuit Design Engineer in CMO, you will be responsible for architecting, designing, and delivering SRAM compilers across high-density (HD) and high-performance (HP) profiles. You will also collaborate with Intel’s Technology Development (TD) group on Design and Technology Co-Optimization (DTCO) to co-define the silicon process and physical layout rules.
What you will do
- Provide industry competitive SRAM design solutions to meet challenging memory design specs for various product segments.
- Design, validation, and characterization of Memory Compilers.
- Memory Compiler Design Flow and Methodology development.