TD Memory Quality and Reliability Engineer

Intel, US, California, Folsom +2

What you will do

Plan and execute SRAM, RF, and/or Fuse technology certification supporting technology development and certification milestones.
Define and maintain certification methodologies and criteria, test strategies, and readiness requirements for memory array.
Drive memory array characterization across multiple operating conditions to evaluate Vmin, Vmax, aging behavior, variability, and design margins.
Analyze silicon characterization data to identify performance gaps, failure signatures, systematic trends, and technology risks.
Develop, validate, and maintain silicon-based Vccmin and Vmax predictive models used for technology certification, PDK releases, and product guidance.

Intel, US, California, Folsom +2

$156K–$255K

a year

This base pay is near the median for infrastructure, platform and SRE jobs in the Bay Area with no level in the job title.

We compare the middle of each posted range. This is base pay as posted. The group does not include this job.

The Intel site opens in a new tab.

Compare your résumé with this job. See where you match, what is missing and which lines to change.

Plan and execute SRAM, RF, and/or Fuse technology certification supporting technology development and certification milestones.
Define and maintain certification methodologies and criteria, test strategies, and readiness requirements for memory array.
Drive memory array characterization across multiple operating conditions to evaluate Vmin, Vmax, aging behavior, variability, and design margins.
Analyze silicon characterization data to identify performance gaps, failure signatures, systematic trends, and technology risks.
Develop, validate, and maintain silicon-based Vccmin and Vmax predictive models used for technology certification, PDK releases, and product guidance.