Platform Integration Engineer

Intel, US, California, Santa Clara

What you will do

Develop logic designs, register transfer level (RTL) coding, and simulation for IP blocks and subsystems for integration into full chip designs
Define architecture and microarchitecture features and ensure their implementation in the design
Optimize design logic to meet power, performance, area, and timing goals while maintaining physical implementation integrity
Review verification plans and address RTL test failures to ensure accurate validation of design features
Collaborate with physical design teams to address floorplan limitations and integrate designs seamlessly
Drive quality assurance compliance to enable smooth IP-to-SoC handoff

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related STEM field with 6+ years of experience with RTL design and SystemVerilog OR Master's degree in relevant field with 4+ years of experience with RTL design and SystemVerilog

Intel, US, California, Santa Clara

Develop logic designs, register transfer level (RTL) coding, and simulation for IP blocks and subsystems for integration into full chip designs
Define architecture and microarchitecture features and ensure their implementation in the design
Optimize design logic to meet power, performance, area, and timing goals while maintaining physical implementation integrity
Review verification plans and address RTL test failures to ensure accurate validation of design features
Collaborate with physical design teams to address floorplan limitations and integrate designs seamlessly
Drive quality assurance compliance to enable smooth IP-to-SoC handoff

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related STEM field with 6+ years of experience with RTL design and SystemVerilog OR Master's degree in relevant field with 4+ years of experience with RTL design and SystemVerilog