ASIC Verification Engineer
Broadcom, USA-Colorado-Fort Collins-4380 Ziegler Road +1
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What you will do
- Testbench Design & Implementation: Architect and develop robust, scalable, and reusable verification environments using SystemVerilog and UVM. Create modular components including reference models, checkers, monitors, scoreboards, and targeted firmware code.
- Verification Strategy & Execution: Author detailed verification plans by analyzing architectural specs. Develop, execute, and debug directed and constrained-random test cases to validate complex ASIC IP blocks.
- Coverage Closure & Quality Assurance: Track, analyze, and maximize functional and code coverage metrics. Write SystemVerilog Assertions (SVA) to implement assertion-based verification and trap corner-case design bugs.