RTL integration Engineer
Broadcom, USA-CA San Jose Innovation Drive
The role
The candidate will be required to perform IP integration and IP test/debug mode verification at the SoC level. This role involves creating RTL designs, performing linting, and executing CDC and RDC analysis for both RTL and gates. Additionally, the candidate will handle synthesis, palladium modeling, and STA support. Strong debugging skills are highly required.
What you need
Requirements
- Extensive knowledge of implementation, synthesis, and timing issues.
- Strong understanding of UVM and SystemVerilog is required.
- Deep familiarity with zero-delay and SDF simulations, including the ability to debug failures effectively.
- Proven experience in gate-level simulation (GLS).
- Familiarity with Clock Domain Crossing (CDC) analysis for both RTL and gate-level designs.
- Highly desirable experience with simulation tools such as NCSim and VCS.
- Ability to work independently with minimal supervision.
- Experience working within a global team and a dynamic environment.