ASIC Physical Design Engineer

• Utilize commercial and in-house EDA tools (e.g. Synopsys, Cadence, Siemens) for the design and implementation of 100 ~ 400 million gate integrated circuits in 7nm/5nm/3nm/2nm process technologies.
• Able to handle a full RTL to GDS or Gates to GDS flow, inclusive of all construction stages (e.g. RTL synthesis, placement, clock tree synthesis, detailed routing, physical verification, formal verification and timing analysis).
• In-depth knowledge of GPU/CPU/DSP architecture/algorithm and related physical design implementation techniques is highly advantageous.
• Proficiency in UNIX/Linux and scripting languages is advantageous.

• Degree, Masters or PhD in Electrical/Electronics/Computer engineering.
• Minimum of 8 years or more experience in a relevant field.

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