- B.Tech in Electronics/Electrical engineering with 3+ years of experience
- Hands-on experience in I/O Library and Analog Mixed-signal IP development and verification
- Solid understanding of Planar and FinFET layouts and process technology
- In-Depth knowledge of ESD and Latch-up principles for I/O and Analog layouts
- Proficiency in using Cadence Virtuoso Layout suite and Siemens CALIBRE verification tools.
- Expertise in Layout verifications and debugging: DRC/LVS/ANT/ERC/DFM, LPE, PERC, EM and IR etc
- Familiar with the Physical Design flow: LEF generation and PnR
- Knowledge of AI, automation in layout, Script Programming and SKILL Programming is a plus.
- Excellent written and verbal communication skills to collaborate with circuit designers and teams across all sites
- Self-motivated, capable of working independently, and a strong collaborative team player.
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