Digital Design Verification Engineer
Broadcom, USA-CA San Jose Innovation Drive +1
The role
The ideal candidate has a proven track record of working on setting up testbenches for Design Verification using UVM on large designs.
What you will do
- Operate with a high degree of autonomy, taking designs from initial specification through to timing closure and physical design hand-off
- Collaborate cross-functionally with Architecture, Verification, and Physical Design teams to mitigate risks and ensure project milestones are met on schedule
- High proficiency in UVM
What you need
- BSEE required, MSEE/PHD preferred
- 5+ years of industry experience with a focus on SoC integration, UVM test bench setup and design debug.