Memory Layout Design Engineer

• Understand and apply layout guidelines, new process rules, and technical requirements for high-quality layouts.
• Manage scheduling, timelines, and layout floor-planning.
• Ensure end-to-end deliverables are completed with high quality and within the planned schedule.
• Adapt quickly to new methodologies and communicate effectively with the SOC and library teams.

Job Requirements

• Minimum 8+ years of experience with a Bachelor's degree or 6+ years of experience with a Master's degree, strong layout knowledge.
• Proficiency in using Cadence tools (Virtuoso Layout, Layout XL, Cadence Schematic Capture, and verification tools - Calibre & Hercules).
• Strong layout knowledge in advanced submicron FinFET processes, including TSMC 5nm, 3nm, 2nm, A14 or Samsung lower FinFET nodes.

Skill Set(Memory)

• Proven ability to manage schedules, timelines, and end-to-end deliverables.