- Master’s or Ph.D. in Electrical Engineering, or a related field (or equivalent experience).
- 5+ years of experience in physical design, DTCO or technology pathfinding.
- Strong background in advanced-node silicon design and physical-design methodology.
- Ability to analyze physical implementation constraints and develop technology solutions to improve PPA.
- Proficiency with Python, Tcl, Perl, or similar scripting languages, as well as AI tools.
Ways to stand out from the crowd
- Experience with DTCO or technology pathfinding for high-performance CPUs, GPUs, or AI accelerators.
- Expertise in advanced circuit and physical-design optimization, clocking, memory, or timing-closure techniques.
- A track record of translating test-chip or silicon data into measurable product improvements.
- Strong technical leadership, with the ability to collaborate across organizations and turn complex technical trade-offs into clear recommendations.
Widely considered to be one of the technology world’s most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family www.nvidiabenefits.com/
Your base salary will be determined based on your location, experience, and other objective job-related factors. The expected base salary ranges for this position are: 136,000 USD – 218,500 USD for Level 3; and 168,000 USD – 264,500 USD for Level 4.
You will also be eligible for equity and benefits.
Applications for this job will be accepted at least until November 3, 2026.
This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.