CPU Physical Design Engineer - Full Time

Rosaic Labs, Santa Clara, CA +1

What you will do

Analyze CPU microarchitecture (pipeline stages, execution units, cache hierarchy, branch prediction) to guide implementation tradeoffs on timing, power, and area
Develop and own gate-level design for CPU blocks: standard-cell selection, logic restructuring, and clock-domain/reset architecture
Perform transistor-level design and custom circuit work for critical-path structures (register files, custom datapaths, memory arrays, high-speed logic)
Drive logic synthesis, floorplanning, power planning, placement, clock-tree synthesis (CTS), and routing to closure
Own static timing analysis (STA), signal integrity, IR drop/electromigration analysis, and physical/electrical signoff

Rosaic Labs, Santa Clara, CA +1

$125K–$250K

a year

This base pay is above the median for hardware and robotics jobs in the Bay Area with no level in the job title.

We compare the middle of each posted range. This is base pay as posted. The group does not include this job.

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Analyze CPU microarchitecture (pipeline stages, execution units, cache hierarchy, branch prediction) to guide implementation tradeoffs on timing, power, and area
Develop and own gate-level design for CPU blocks: standard-cell selection, logic restructuring, and clock-domain/reset architecture
Perform transistor-level design and custom circuit work for critical-path structures (register files, custom datapaths, memory arrays, high-speed logic)
Drive logic synthesis, floorplanning, power planning, placement, clock-tree synthesis (CTS), and routing to closure
Own static timing analysis (STA), signal integrity, IR drop/electromigration analysis, and physical/electrical signoff