Physical Design Engineer
Fortell, San Francisco Bay Area, CA
The role
We're looking for an experienced Physical Design Engineer to help bring our next-generation custom ASICs from RTL to silicon. You'll play a critical role in delivering high-performance, low-power silicon that powers our AI-enabled hearing platform, while helping evolve the methodologies and flows that enable our engineering team to scale.
What you will do
- Execute synthesis, PNR, and STA for assigned partitions of ASIC chip adhering to strict schedules and design goals.
- Work closely with architects, RTL designers, and DFT engineers to resolve implementation and signoff issues across your blocks.
- Help close EM/IR, drive LEC and physical verification signoff for your partitions in coordination with methodology owners.
- Partner with the design team to proactively identify and address potential physical design challenges, enabling efficient iteration and convergence.