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The role
RosaicLabs is seeking a Reliability, Availability, and Serviceability (RAS) Architect to define resilience across its multi-die computing systems. This person will turn reliability targets into hardware, firmware, and software requirements for fault detection, error containment, recovery, silent-data-corruption prevention, and actionable fleet telemetry.
What you will do
- Own the end-to-end RAS specification, reliability and availability targets, FIT budget by domain, common error records and timestamps, and software-visible error-bank mapping where applicable.
- Define fault detection, correction, logging, and diagnosis across compute engines and cores, caches, HBM and LPDDR memory, die-to-die and scale-up links, PCIe/CXL, and management agents.
Nice to have
- Familiarity with processor and uncore error-reporting architectures, firmware-first error handling, BMC integration, or fleet reliability telemetry.
- Experience with silent-data-corruption analysis, in-field screening, or graceful degradation of large multi-die systems.
- Ability to drive the microarchitecture of RAS logic blocks such as error banks, poison paths, injection controls, and recovery state machines.
Eligibility In compliance with federal law, all persons hired will be required to verify identity and eligibility to work in the United States and to complete the required employment eligibility verification form upon hire. Visa sponsorship is available for this role for qualified candidates.
Minimum Education and Experience
- Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent practical experience.
- At least 12 years of experience in SoC architecture, design, verification, silicon validation, or platform reliability, including at least 3 years defining or leading RAS features for a processor, accelerator, or server-class SoC.
- Experience carrying a RAS feature from architecture specification through design and verification to silicon bring-up or production deployment.
- Working knowledge of ECC or parity, error logging, poison handling, fault injection, containment, and recovery, including how hardware error behavior is exposed to firmware and software.
- Experience across at least two of these domains: compute and cache subsystems; HBM, DDR, or LPDDR memory; interconnects; or PCIe, CXL, and high-speed links.
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Source: the Rosaic Labs Lever job board. We last checked this job 19 h ago. We first saw it 31 h ago. A job on a job board does not always mean that the team interviews people now. We found this job board in a public list. We did not yet compare it with the careers page of the company.
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