Wafer Architect

We’re looking for an architect to own the logical architecture for the A-0 and A-1 wafer products. You will work with the XPU/Compute chip architect and the memory architect to synthesize the final wafer-level architecture.

Ideal Background

An ideal candidate will have

• Deep understanding and hands-on experience in the design process of AI chips, such as GPUs, TPUs, XPUs, custom ASICs, etc
• Understanding of memory sub-systems and interactions in multi-die systems
• Understanding of LLM inference workloads, especially at a software level and its implications for hardware (system, package, network, die-level) systems

Strongly Preferred

• Experience with multi-die designs
• Experience with MCM and chiplet based architectures and architectural partitioning across them
• Experience in partitioning workloads across multiple chips and chip packages