Rust SW-Silicon Co-verification Engineer

We aim for zero hardware bugs in our chips. A bad bug can cost us millions of dollars, so we invest heavily in correctness. You'll be part of this investment.

In addition to the hardware design for our chip ("the RTL"), we have a cycle-accurate microarchitectural simulator ("the sim," written in Rust) created from the same spec by a different team.

In this role, you will perform differential testing between the RTL and the sim: generate inputs, check that the RTL and sim agree with each other, and, when possible, check that they both agree with properties guaranteed by the spec.

You'll also do performance work on the sim itself and on technologies for simulating RTL.