Senior/Staff/Principal IC Layout Engineer – Optical Engine Silicon

• Diploma, BS, or MS in Electrical or Electronics Engineering, or equivalent hands-on layout experience.
• 8+ years in custom analog, RF, or high-speed mixed-signal IC layout, including multiple tape outs you saw through to silicon.
• Expert-level Cadence Virtuoso, including Layout XL and constraint-driven flows.
• Deep parasitic awareness – you can look at a schematic and a spec and know which nets will decide whether the block works.
• Working command of electromigration and IR drop fundamentals: current density limits, power grid design, and the checks that sign them off.
• Electromagnetics fundamentals for on-chip structures — inductors, transformers, transmission lines, coupling, and shielding.
• Physical verification fluency: Calibre or PVS DRC/LVS, and parasitic extraction with QRC, StarRC, or equivalent.
• Willingness to overlap with US and India hours during tapeout crunch.

• SiGe BiCMOS layout experience, and the passive and isolation practices those processes demand.
• Advanced FinFET CMOS layout at 7nm and below — multi-patterning and coloring, fin and poly grid constraints, and the DRC complexity that comes with them.
• Photonic IC layout exposure: waveguide routing, curvilinear geometry, and photonics PDK design rules.
• Hands-on silicon photonics layout on a foundry platform (Si and SiN waveguides), including PCell development in Virtuoso SKILL or Python-based photonic layout tools (gdsfactory, KLayout, IPKISS).
• Understanding of how layout drives photonic performance — propagation loss, phase error, optical and thermal crosstalk.
• 2.5D and 3D integration, interposers, micro-bump and copper pillar arrays, and co-packaged optics assemblies.
• Layout for optical front ends specifically — TIA, modulator driver, or high-speed serial link blocks.
• Experience standing up layout methodology for a product line in its first generation, where nothing existed yet.
• Scripting for layout automation – SKILL, Python, or both.

Why this role

Optical I/O for AI is being defined right now, and in this silicon the layout is where the performance is actually won — these are blocks where a few femtofarads and a poorly planned return path decide whether the link closes. You will have real authority over physical design on parts going into production at scale, short lines to the designers whose circuits you are building, and a founding hand in how our Singapore silicon team works.

• Own floorplan and layout for high-speed analog and mixed-signal blocks: TIAs, drivers, SerDes front ends, PLL and clocking, references and bias.
• Execute device-level matching and symmetry — common-centroid, dummies, shielding, guard rings, substrate isolation — to the level these circuits actually require.
• Route high-speed signal paths with control over impedance, coupling, and return paths. Lay out passive and electromagnetic structures (inductors, transformers, transmission lines) and work with designers through EM simulation.
• Own chip finishing: pad ring, bump and pillar maps, seal ring, density fill, and top-level assembly through tape out.

• Drive parasitic-aware layout: iterate with designers on extraction results and close the loop between what the schematic assumed and what the layout delivers.
• Own electromigration and IR drop closure — current density, power grid construction, and the analysis that proves it holds at temperature and lifetime.
• Take blocks through DRC, LVS, antenna, DFM, and ESD and latch-up checks to sign-off.

• Support PIC layout as the need arises: waveguide and curvilinear structures, and the design rules that come with a photonics platform.
• Own layout of photonic blocks: waveguide routing under bend-radius, spacing, and length-matching constraints; modulator (MZM, ring) and photodetector electrode layout co-optimized with the RF drive path; and grating and edge coupler placement against fiber-attach and packaging constraints.
• Build and maintain the photonic PCell library and PDK integration in Virtuoso — curvilinear geometry generation, SKILL and Python automation, grid snapping and stream-out, and DRC/LVS methodology for custom photonic cells.
• Own the EIC-PIC integration — micro-bump and pillar alignment, interposer interfaces, and the co-layout decisions that make the electrical path work across two dies.

• Set layout standards here: reusable structures, PDK and tech file evaluation, automation, documentation, and review practice.
• Mentor junior layout engineers as the Singapore team grows, and represent layout in design reviews with real authority.