Member of Technical Staff, Performance Modeling

About the role

We are seeking a Member of Technical Staff, Functional and Performance Modeling to develop functional and performance models for our scale-up network-attached memory expansion device for AI accelerators.

You’ll work as part of our silicon architecture team to perform functional and performance modeling. You should have experience exploring design tradeoffs, validating performance assumptions, and identifying bottlenecks early in the development cycle. This role is well-suited for engineers who enjoy reasoning from first principles, working with incomplete information, and co-exploring the design space as hardware and software evolve together.

This role will be performed onsite from one of our offices in Santa Clara, CA or Boston, MA.

The opportunity

• Impact: AI is advancing faster than the infrastructure underneath it. We’re working at that layer, unlocking more capability from every GPU while dramatically improving efficiency. The work you do here compounds across state-of-the-art models, systems, and real-world applications.
• Timing: Joining now means real ownership, including equity, and a direct say in product direction. You’ll work from first principles, move quickly from insight to execution, and see your work show up in what we ship, not just in a roadmap.
• Culture: We care about rigor, clarity, and impact. Disagreement is welcome when it’s thoughtful, the best idea wins regardless of who it comes from, and you’ll learn something new most weeks.

• Build and maintain system-level (e.g., rack-scale) and chip-level performance models for high-bandwidth data movement between devices operating in the scale-up domain.
• Model workloads from software memory access patterns through data distribution in the network and all the way down to on-device memory channels.
• Work day-to-day with silicon architects, system designers, and workload owners to align performance expectations and constraints.
• Identify performance bottlenecks, scaling limits, and sensitivity points across compute, memory, and interconnects in end-to-end workload settings.
• Clearly communicate modeling assumptions, limitations, and conclusions to both technical and non-specialist stakeholders.

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a closely related field.
• 5–10+ years of experience in performance modeling for data movement devices: NICs, memory expansion cards (e.g. CXL), IPU/DPU, NoC.
• Ability to reason across multiple abstraction layers, from architectural details to system-level performance behavior.

• Prior experience modeling performance for networking protocols with memory semantics.
• Familiarity with shared memory systems and frameworks (e.g. CUDA VMM).
• Familiarity with modern AI/ML technical stack from a workload perspective: large language model inference and sharding, KV caching, serving system (e.g., continuous batching).
• Experience with scale-up and high-bandwidth interconnects (e.g. NVLink or similar technologies).
• Experience with modeling memory subsystems

• Competitive salary with performance-based bonus and early-stage equity grant
• 100% employer-paid Health, Dental, and Vision coverage for you and your dependents
• 401(k) match with immediate vesting, and access to financial advisors to help you reach your financial goals
• 100% employer-paid Life, Disability, and AD&D insurance, plus a fitness stipend and wellness & mental health perks
• Generous PTO: 20 vacation days, 15 company holidays (including 3 floating days of your choosing)
• Daily lunch stipend
• Enterprise-level Claude & ChatGPT access with a generous token budget
• Well-equipped, sunny offices in Santa Clara, CA & Cambridge, MA with on-site parking and EV charging; on-site fitness center in Santa Clara; gym discounts near our Cambridge office
• Visa sponsorship and relocation assistance to one of our office hubs
• A collaborative, continuous-learning environment with smart, dedicated colleagues building the next generation of high-performance computing architecture

The biggest bottleneck in AI systems today is memory. Chips compute faster than they can be fed data—a problem known as the memory wall—and Netpreme is building the solution that allows AI memory to scale independently of AI compute. Our approach spans the full stack, from a proprietary memory management framework at the XPU kernel and OS levels to X-Mem™, the world’s first Memory Processing Unit (MPU) silicon. Founded by MIT researchers at the intersection of optical networking, ML systems, and GPU kernel optimization, we’re based in Cambridge, MA, and Santa Clara, CA.

We’re looking for people who want to own hard problems end to end—and help shape the next generation of AI systems.

Click here https://netpreme.com/blogto read our latest blog!