Senior High Speed IO Validation Engineer

NVIDIA’s Silicon Co-Design Group is the team that gets every GPU, SoC, and CPU silicon program from first power-on to high-volume production. We are hiring an HSIO Validation Engineer to own characterization and qualification of high-speed I/Os — PCIe, NVLink, NVLink-C2C, UCIe, USB, UFS, and Ethernet — on brand-new silicon serving datacenter, AI, and client markets. Your bench is where silicon meets the signal — where every link train, jitter sweep, eye diagram, and protocol corner gets exercised before the part ships.

You drive characterization and debug for IO interconnects across silicon, board, firmware, and driver — designing tests that anticipate rack-scale deployment so marginality surfaces at die-and-board scale, never in a rack. Your decisions show up in link margin, BER, power per lane, and the go/no-go calls that gate samples and production.