Head of Silicon Product Engineering

• Post-Silicon Strategy: Own end-to-end bring-up, characterization, validation, and debug across multiple silicon generations.
• Packaging & Test: Define and drive packaging and test strategy, including ATE program development, test coverage, and test condition optimization for yield, quality, and performance.
• OSAT & Test-House Selection: Select, qualify, and manage OSAT and test-house partners; own the relationship through NPI and into high-volume manufacturing, including cost, quality, and yield negotiations.
• Yield & Qualification: Lead yield learning and qualification efforts from early silicon through production ramp, including root-cause analysis of systematic and random failures.
• Production Calibration & Screening: Own production calibration and screening methodology for our memory products, ensuring performance and reliability targets are met at volume.
• Team Build: Build and lead a high-performing silicon product engineering organization from the ground up, including hiring, process, and tooling.
• Cross-Functional Feasibility: Partner closely with design, architecture, and supply chain teams to ensure designs are producible, testable, and optimized for cost and yield before they become expensive to change.
• Data Infrastructure: Build the data analysis practices needed to catch failure mechanisms early: characterization and manufacturing data from wafer acceptance testing, sort, package, and system-level test.

• 15+ years in semiconductor product/test engineering, with direct ownership of silicon from NPI through high-volume manufacturing.
• Proven experience selecting and managing OSAT and foundry partners, including cost, quality, and yield negotiations.
• Deep hands-on background in packaging, ATE, and post-silicon bring-up and validation.
• Experience with production test and screening methodology for complex, high-reliability products.
• A track record of building and scaling engineering teams from early stage.
• Strong cross-functional fluency with design, architecture, and supply chain organizations.
• Bachelor’s or Master’s degree in Electrical Engineering or a related field.

• Experience bringing up test and qualification for a new or unconventional silicon architecture, not just a new generation of a familiar one.
• Experience with memory-adjacent product engineering (DRAM, HBM, or custom memory modules).
• Experience at an AI or high-performance compute startup where design, verification, and product engineering worked in tight iteration cycles.
• Comfort operating in an environment where the test methodology is still being invented alongside the hardware.

Normal is an applied AI company solving the hardest problems in AI and silicon. We build foundational hardware and software for the semiconductor industry, critical AI infrastructure, and the broader systems that power our world, in partnership with the world's most advanced institutions. We work as one team across New York City, Silicon Valley (Mountain View), and London.