Tech Lead, STA
Astera Labs, Hyderabad, Telangana, India +1
What you will do
- Full-Chip STA Signoff & Timing Closure
- Own end-to-end top-level STA signoff across multiple modes, corners, and operating conditions (MMMC) for complex AI connectivity SoCs
- Drive timing convergence on advanced process nodes (5nm/4nm/3nm and below) from early floorplan through tapeout
- Analyze and resolve setup, hold, recovery/removal, and clock-domain crossing (CDC) timing violations at the chip level
- Methodology & Flow Development
- Define and evolve STA methodology, constraints (SDC) strategy, and signoff criteria across the organization
- Develop and automate flows using PrimeTime, PrimeTime SI, and related signoff tools for crosstalk, noise, and IR-aware timing
- Establish best practices for hierarchical STA, ETM/IPXACT model generation, and budgeting across blocks