Formal Validation Engineer

APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Work on the complete formal verification for single or multiple design blocks and IP's (CPU, Cellular and Connectivity IP, Audio and Image Processing IP, Neural Networks IP, Memory/OMA Controller, Security IP, Peripheral IP, Interconnects, Power management subsystems, etc.). Work with Apple Silicon's world-class SOC and IP design engineers to develop a formal microarchitecture specification Develop comprehensive formal verification test plan.

Prove properties of the design, find design bugs, and work closely with design teams to help improve the micro-architecture. Craft novel and creative solutions for verifying complex design micro-architectures. Develop and implement re-usable and optimized formal models and verification code base. Responsible for architecting correct-by-construction design methodologies for improved formal verification efficiency and productivity. 40 hours/week.