VLSI CAD Engineer

APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Execute RTL regression tests using industry-standard verification tools like Verilog/System Verilog HDL simulators and system verification languages (e.g., UVM). Monitor regression results, analyze coverage data, and identify failed tests. Use coverage tools to measure and enhance functional coverage. Collaborate with the DV team to understand the root causes of regression failures.

Utilize debuggers to step through RTL code and identify issues. Develop and implement new solutions to address regression issues, enhance verification efficiency, or optimize computer usage using ML-based techniques. Build ML models that predict test failures or optimize resource allocation. Implement performance optimizations in regression runs using tools like task parallelism libraries or cloud-based verification platforms. Maintain and enhance the existing RTL regression system to ensure its reliability and efficiency.