FE Engineer

APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Work on front-end design synthesis and large chip integration. Work timing analysis, formal verification, and lint checks. Design multi-clock and multi-power-domain. Understand floor-planning, placement, congestion, and setup/hold timing closure and working hands on with ECOs for functionality and timing. Propose logically equivalent RTL transforms to reduce power and area.