FE Engineer

APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Work with other specialists that are members of the SoC Design, Soc Design Verification, System Verification, STA, and Physical Design teams to implement designs/flows for sophisticated Socs. Integrate various IPs and ensure design meets DFT (design-for-test), CDC (clock domain crossing), Synthesis/Static Timing and Power Requirements.

Work with CAD and Flow teams to define and improve front-end design methodologies. Develop micro-architecture and design specifications. Implement and verify sophisticated logic designs. Work with designers on STA, physical, power and logical issues. Participate in meetings, discussions, and writing documentation to ensure clear communication and thorough understanding of design requirements and progress. Develop RTL design of one or more blocks following established design guidelines based on microarchitecture spec.