Physical Design Timing Engineer
DensityAI, Mountain View, CA +1
The role
Own Full chip and Block timing methodologies and execution to-signoff of our AI accelerator silicon. Work with chip-design and software teams driving DensityAI's AI accelerator program from first silicon through scale-out.
What you will do
- Own Full chip and Block timing methodologies and execution to-signoff of our AI accelerator silicon.
- Use and develop AI-assisted tool flows to accelerate physical design timing convergence and signoff timelines.
What you need
- Exceptional abilities across the full physical design flow (synthesis, place & route, CTS, signoff) with emphasis on timing flows and methodologies