Lead Digital Verification Engineer

Efficient Computer, San Francisco, Bay Area OR Pittsburgh, PA OR Austin, TX +3

The role

We are looking for an experienced Design Verification Lead to drive the functional verification of complex SoC/IP designs from specification through tapeout in a newly formed hardware engineering organization. You will own the verification strategy, define methodology standards, build and guide a team of verification engineers, and serve as the final authority on verification quality and sign-off readiness. This role demands a strong blend of technical depth in modern verification methodologies (UVM, embedded C and compiler generated trace driven testing) and the leadership ability to execute across a multi-block chip program on schedule The DV Lead will help shape our internal processes for building robust and verified designs, including the company’s second product line, which will scale computing performance and capability, while improving energy efficiency.

This is a unique opportunity to have an influence on our products and processes as we move from the initial stages of product development to market release and scaled volume production. Join our team and help us shape the future of computing at the edge and beyond!

All jobs

Lead Digital Verification Engineer

Efficient Computer, San Francisco, Bay Area OR Pittsburgh, PA OR Austin, TX +3

The role

What you will do

Define the end-to-end verification strategy across block, subsystem, and full-chip levels aligned with tapeout milestones
Author and review verification plans mapping specifications to features, stimulus strategies(traditional stimulus generation, compiler driven), coverage goals, and sign-off criteria
Architect scalable UVM-based testbench environments including agents, scoreboards, reference models, and coverage monitors
Drive constrained-random stimulus development targeting protocol interactions, concurrency, error injection, and corner cases
Define and close functional coverage models through systematic hole analysis, targeted tests, seed optimization, and regression tuning
Deploy SystemVerilog Assertions for protocol compliance, interface checks, and design invariants across all simulation runs
Lead full-chip verification including boot sequences, interrupt handling, DMA flows, power-on reset, and multi-block interactions
Ensure CDC, RDC, and multi-power-domain verification in coordination with specialist tools and teams
Debug complex simulation failures spanning multi-block interactions, protocol violations, race conditions, and timing-dependent corner cases
Own the bug lifecycle – triage, prioritization, tracking, fix verification, and cross-functional resolution with RTL designers and architects
Manage the regression framework – defining suites, maintaining stability, optimizing throughput, and integrating with CI/CD pipelines
Coordinate simulation-to-emulation handoff ensuring verification collateral transitions effectively to emulation environments
Collaborate cross-functionally with Compiler Team, RTL design, DFT, physical design, and post-silicon validation teams
Lead, mentor, and grow the verification engineering team while maintaining a high quality bar through rigorous reviews
Represent verification readiness in tapeout sign-off reviews and program-level decisions
Support running gate-level simulations as part of design signoff.
Assist in building a verification dashboard to quickly understand where a design is in the verification process and to identify regressions.

What you need

Education: Bachelor's or Master's/PhD degree in Electrical Engineering, Computer Engineering, or a related field.
Experience: 10+ years of progressive experience in ASIC/SoC design verification, with at least 3 years in a lead role owning verification strategy, sign-off, and team execution.
UVM Mastery: Deep expertise in UVM-based testbench architecture and constrained-random verification methodology — not just usage, but architectural decision-making and optimization.
SystemVerilog: Advanced proficiency in SystemVerilog for verification including classes, constraints, functional coverage, assertions (SVA), interfaces, and packages.
Coverage Closure: Demonstrated track record of driving functional and code coverage to tapeout sign-off on complex, multi-million-gate SoC/ASIC designs.
Debug Skills: Proven ability to debug deeply complex simulation failures spanning multiple design blocks, protocols, and abstraction levels.
SoC Architecture: Strong understanding of modern SoC building blocks — processors (ARM, RISC-V), interconnects (AMBA AXI/ACE/CHI), memory controllers, DMA engines, interrupt controllers, and standard peripherals.
Scripting & Automation: Proficiency in Python, Perl, or Tcl for test automation, log analysis, coverage post-processing, and regression flow development.
Communication: Clear and effective communication of verification status, risk, and trade-offs to technical peers and program leadership.

We offer a competitive base salary for this role, generally ranging from $200,000 to $260,000, plus a 10% annual bonus, meaningful equity, and comprehensive benefits. Final compensation will depend on experience, level, and location, with flexibility for the right candidate.

Why Join Efficient?

Build what's next. At Efficient, you'll tackle big challenges with room to take ownership and make an impact. We back you with competitive pay, equity, a 401(k) match, company-paid benefits, paid parental leave, and flexibility—plus opportunities to grow your skills and career as we scale.

Lead Digital Verification Engineer

The role

Lead Digital Verification Engineer

The role

What you will do

What you need

About Efficient Computer

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