Architect and implement IP or subsystem-level UVM verification environments, including monitors, scoreboards, checkers, and reusable verification components. Collaborate with architects, hardware designers, and firmware teams to define and verify new PCIe, CXL, and high-speed connectivity features. Develop comprehensive verification plans that address feature interactions, hardware/software integration, performance requirements, and system-level use cases.
Develop directed and constrained-random tests, execute regressions, and debug failures to ensure high functional coverage and design quality. Drive verification automation, methodology improvements, and adoption of AI-assisted tools to improve development efficiency and productivity. PREFERRED EXPERIENCE: ASIC/IP verification experience using UVM methodology. Strong expertise in SystemVerilog, Verilog, object-oriented programming, and UVM-based verification environments.
Experience verifying high-speed protocols such as PCIe, CXL, Ethernet, PCIe Gen6, or 400G Ethernet. Proficiency in scripting and automation using Python, Perl, or similar languages. Experience working across the ASIC/FPGA development lifecycle from planning through tape-out. Exposure to performance verification, simulation optimization, acceleration technologies, HLS tools, or verification efficiency improvements. Technical leadership, mentoring experience, and strong communication skills within geographically distributed teams.
Knowledge of computer architecture, system-level design concepts, and emerging AI-driven verification methodologies is a plus. ACADEMIC CREDENTIALS: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field. LOCATION: San Jose, CA This role is not eligible for visa sponsorship.