ASIC Timing Engineer
Etched, Cupertino, CA +1
The role
Etched is seeking an exceptional ASIC Timing Engineer to join our innovative team. The candidate will be responsible for driving timing analysis and closure of our next-generation AI chips, ensuring that we meet the high-performance demands of our unique architecture.
Representative Projects
- Drive timing analysis and closure of chips at block, cluster, and full chip level
- Collaborate with Physical Design, DFX, Clocks, and other teams to develop timing closure strategies, create timing constraints, and ensure timing and power convergence, as well as ECO implementation
- Enhance timing convergence flows in partnership with our methodology teams
- Contribute to DFT logic understanding and assist with DFT timing closure for various modes, such as scan and BIST
- Work on timing closure of digital logic/macros in AMS designs/IPs, ensuring all aspects are addressed