Senior STA Engineer

NVIDIA is seeking a Physical Design and Timing Engineer to join our silicon implementation team. This role focuses on timing analysis, timing closure, and signoff quality across complex ASIC and SoC designs. You will work closely with physical design, front-end design, methodology, and CAD teams to drive robust implementation at advanced process nodes. This is a strong fit for an engineer who enjoys deep analysis, problem solving, and improving quality at block and full-chip levels.

• Drive static timing analysis and timing closure for block and/or full-chip designs.
• Develop, review, and debug timing constraints, scenarios, and signoff checks.