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Design Engineer - STA

Broadcom, USA-Colorado-Fort Collins-4380 Ziegler Road

Broadcom has this job in 1 other place

USA-Colorado-Fort Collins-4380 Ziegler Road

Posted pay

$129K–$207K

a year

Location: USA-Colorado-Fort Collins-4380 Ziegler Road
Work type: Not given
Level: Not given
Experience: 12+ years
Skills in the job text: Python
Linux
Ruby
Posted: 13 days ago
Last check: 2 h ago
Job type: Software engineering

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Broadcom

About Broadcom: funding, hiring and pay

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The role

Be part of the Custom Silicon Design Team within Broadcom’s ASIC Products Division in beautiful Fort Collins, Colorado. Join a world-class engineering group developing custom CMOS ASICs for cutting-edge AI, Cellular, Networking, Computing, and Storage products. This position offers the opportunity to work on high-performance SoC designs operating at speeds exceeding 1 GHz, from concept through production.

Role Overview

This STA Engineering role focuses on chip-level timing architecture, analysis, and closure for advanced ASICs in deep sub-micron technologies. The position provides hands-on experience with the latest 3 nm and smaller process nodes and involves working across multiple design hierarchies to define, validate, and sign off complex timing environments for AI, computing, and networking SoCs.

What you will do

Develop, validate, and maintain timing constraints for complex SoC designs across multiple modes and corners.
Perform static timing analysis (STA) using industry-standard tools such as Synopsys PrimeTime or Cadence Tempus.
Define and execute timing signoff methodologies, including process corners, derates, and uncertainties.
Conduct pre- and post-route timing analysis, quality of results (QoR) evaluations, and closure verification.
Generate and validate timing ECOs to achieve signoff-quality closure across PVT corners.
Automate timing flows and analysis using Tcl and scripting languages such as Perl or Python.
Collaborate with physical design, synthesis, and clock teams to ensure timing convergence and cross-domain consistency.
Analyze and debug timing violations, signal integrity issues, and clock network challenges.
Support power and performance optimization through informed timing analysis and constraint tuning.
Ensure full compliance with timing signoff checklists, methodology, and documentation.

What you need

Technical Skills / Background

Deep understanding of VLSI design principles and ASIC physical design fundamentals.
Working knowledge of PLLs, clock network design, and timing elements such as flip-flops, latches, and memories.
Proficiency in timing constraint creation, debugging, and validation.
Strong understanding of RC networks, signal integrity, crosstalk delay, and noise analysis.
Familiar with setup/hold analysis, multi-mode multi-corner (MMMC) timing, and ECO convergence.
Exposure to advanced STA techniques, including POCV/SOCV/LVF, PBA, and SPICE correlation.
Knowledge of timing libraries (CCS/ECSM/NLDM) and multi-input switching (MIS) effects.

Education and Experience

BS in Electrical or Computer Engineering with 12+ years of relevant experience, or
MS in Electrical or Computer Engineering with 10+ years of relevant experience.

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Coding & Tool Proficiency

Strong experience with Tcl scripting and Linux/UNIX environments.
Proficiency in Python, Perl, or Ruby preferred.
Hands-on experience with Synopsys and/or Cadence STA tools highly desirable.

Collaboration and Leadership

Excellent communication, analytical, and problem-solving abilities.
Ability to work effectively with external customers, cross-functional and global design teams.
Skilled at organizing and presenting large data sets, prioritizing tasks, and driving to closure.
Demonstrates independent decision-making and strong engineering judgment.
Provides technical leadership, mentoring, and initiative in methodology improvements.

Pay and benefits

The annual base salary range for this position is USD 129,400.00 To USD 207,000.00

As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Legal notes

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

Read the job posting on the Broadcom site

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Source: the Broadcom Workday careers site. We last checked this job 2 h ago. We first saw it 4 days ago. A job on a job board does not always mean that the team interviews people now.

Broadcom

Open tech jobs: 196
With posted pay: 63%
Median posted base: $122K–$195K

About Broadcom: funding, hiring and pay

Compared with similar jobs

This base pay is near the median for software engineering jobs in other US places with no level in the job title.

Median: $165K a year
Other jobs in the group: 2,887

We compare the middle of each posted range. This is base pay as posted. The group does not include this job.