Front-End Power Engineer

Etched, Cupertino, CA +1

What you will do

Optimize RTL designs to boost power efficiency while meeting performance and area objectives.
Perform power analysis throughout various stages of silicon design, applying power-saving strategies in RTL such as clock gating, power gating, multi-voltage domains, and dynamic voltage scaling.
Conduct power estimation and evaluate PPA trade-offs for both new and existing design features.
Collaborate closely with the physical design team to ensure power targets are met during the synthesis, place-and-route (P&R), and sign-off phases.
Create precise power models from RTL simulations and gate-level netlists, and perform power roll-up analysis to estimate chip-level power consumption under different conditions.

Etched, Cupertino, CA +1

Optimize RTL designs to boost power efficiency while meeting performance and area objectives.
Perform power analysis throughout various stages of silicon design, applying power-saving strategies in RTL such as clock gating, power gating, multi-voltage domains, and dynamic voltage scaling.
Conduct power estimation and evaluate PPA trade-offs for both new and existing design features.
Collaborate closely with the physical design team to ensure power targets are met during the synthesis, place-and-route (P&R), and sign-off phases.
Create precise power models from RTL simulations and gate-level netlists, and perform power roll-up analysis to estimate chip-level power consumption under different conditions.